carry lookahead
英
美
先行进位
双语例句
- In order to raise arithmetic speed and to expand operand bit of the long adders, the structure of top-level carry cascade carry lookahead adders ( TC2CLA) of hybrid modules was presented.
为提高长加法器的运算速度，扩展操作位数，提出了一种加法器结构&混合模块顶层进位级联超前进位加法器（TC2CLA）。 - Algorithm of TC~ 2CLA ( Top-level Carry Cascade Carry Lookahead Adders) and its design rule
顶层进位级联CLA的算法与设计规则 - In order to expand operand bet of the long adders, a general structure of hybrid modules cascade Carry Lookahead Adders ( CLA) was presented.
为扩展操作位数提出了一种更具普遍性的长加法器结构&混合模块级联超前进位加法器。 - Two definitions of carry propagation function and basic circuit unit and three combination scenarios of Carry Lookahead Adders ( CLA) were analyzed for resource ( area), speed and power dissipation in this paper.
从体现资源（面积）、速度、功耗的各个方面分析了超前进位加法器进位传输函数的2种定义和基本单元电路及其3种组合方案。 - Delay Time Formulae and Optimizing Sequence of Hybrid Modules Cascade Carry Lookahead Adders
超前进位加法器混合模块延迟公式及优化序列 - Delay Time Formulae and Optimizing Design of Carry Lookahead Adders
超前进位加法器的延迟时间公式与优化设计 - The hybrid modules cascade Carry Lookahead Adders ( CLA) without waiting time sequence was advanced on the basis of analysis delay time formula of hybrid modules cascade CLA for the purpose of the fullest expanding operand bit of CLA under conditions of not raising delay time of CLA.
在不增加超前进位加法器模块延迟时间的条件下，为最大限度地扩展操作位数，在分析混合模块超前进位加法器（CLA）延迟时间公式的基础上提出了混合模块无等待时间序列超前进位加法器。 - Using Verilog HDL describes the logic function of the system. The carry lookahead adder or subtracter raises the working speed of the circuits.
采用Veriloghdl语言描述了系统的逻辑功能，超前进位结构的加/减法器提高了电路的工作速度。 - The study of a carry lookahead algorithm in the PRNs adder
PRNS加法中先行进位算法的研究 - The logic operations of PD-LED are studied. and experiment of optical parallel carry lookahead adder for many bits is carried out, with satisfactory results.
研究了PD-LED的光电混合逻辑操作，利用PD&LED逻辑器件，从实验上验证了先行进位光学并行多位全加器，获得了满意的结果。